A synchronous dynamic random access memory (SDRAM) is designed to operate in a synchronous memory system. Thus, all input and output signals, with the exception of a clock enable signal during power down and self refresh modes, are synchronized to an active edge of a system clock.
SDRAMs offer substantial advances in dynamic memory operating performance. For example, some SDRAMs are capable of synchronously providing burst data in a burst mode at a high-speed data rate by automatically generating a column address to address a memory array of storage cells organized in rows and columns for storing data within the SDRAM. In addition, if the SDRAM includes two banks of memory arrays, the SDRAM preferably permits interleaving between the two banks to hide precharging time.
In an asynchronous DRAM, once row and column addresses are issued to the DRAM and a row address strobe signal and column address strobe signal are deactivated, the DRAM's memory is precharged and available for another access. Another row cannot be accessed in the DRAM array, however, until the previous row access is completed.
By contrast, a SDRAM requires separate commands for accessing and precharging a row of storage cells in the SDRAM memory array. Once row and column addresses are provided to a SDRAM in a SDRAM having multiple bank memory array's, a bank memory array which is accessed remains active. An internally generated row address strobe remains active and the selected row is open until a PRECHARGE command deactivates and precharges the selected row of the memory array.
In a SDRAM, a transfer operation involves performing a PRECHARGE command operation to deactivate and precharge a previously accessed bank memory army, performing an ACTIVE command operation to register the row address and activate the bank memory array to be accessed in the transfer operation, and performing the transfer READ or WRITE command to register the column address and initiate a burst cycle. At many frequencies, the time to perform the PRECHARGE command operation, and the ACTIVE command operation results in wasted time which adds up to an extra clock cycle resulting in a wait cycle. Thus, there is a need to eliminate possible wasted clock cycles between random READS and writes in a SDRAM.